https://homeostasis.scs.carleton.ca/wiki/index.php?action=history&feed=atom&title=Operating_Systems_2019F_Lecture_8 2026-05-18T21:41:56Z Revision history for this page on the wiki MediaWiki 1.42.1 https://homeostasis.scs.carleton.ca/wiki/index.php?title=Operating_Systems_2019F_Lecture_8&diff=22473&oldid=prev 2019-09-27T21:33:09Z

<p>Created page with &quot;==Video== Video from the lecture given on September 27, 2019 [https://homeostasis.scs.carleton.ca/~soma/os-2019f/lectures/comp3000-2019f-lec08-20190927.m4v is now available]....&quot;</p> <p><b>New page</b></p><div>==Video==<br /> <br /> Video from the lecture given on September 27, 2019 [https://homeostasis.scs.carleton.ca/~soma/os-2019f/lectures/comp3000-2019f-lec08-20190927.m4v is now available].<br /> <br /> ==Notes==<br /> <br /> &lt;pre&gt;<br /> Lecture 8<br /> ---------<br /> <br /> In tutorial 3, you saw mmap. To explain this, we must discuss...<br /> <br /> virtual memory!<br /> <br /> On every memory access, the CPU must<br /> get virtual address<br /> map virtual address to a physical address<br /> read memory (in cache or main memory) from physical address<br /> <br /> this mapping is managed by the MMU (memory management unit)<br /> <br /> No MMU, no virtual addresses<br /> <br /> To really make things fast, we have the fastest cache in the CPU<br /> - the TLB (translation lookaside buffer)<br /> - caches virtual-&gt;physical memory mappings<br /> <br /> because mappings have to be stored in RAM somewhere..the TLB caches them<br /> <br /> What is a cache?<br /> <br /> memory hierarchy<br /> -----------------<br /> <br /> wide range of storage:<br /> * fast and small to large and slow<br /> <br /> VOLATILE<br /> <br /> CPU registers<br /> TLB<br /> level 1 cache<br /> level 2 cache<br /> level 3 cache<br /> main memory (RAM)<br /> <br /> ---<br /> NON VOLATILE<br /> <br /> solid state disk<br /> spinning hard drive<br /> tape drive<br /> <br /> memory hierarchy works as long as we can have high temporal and spatial locality<br /> <br /> spatial:<br /> - accessing one byte means we&#039;ll access nearby bytes<br /> <br /> temporal:<br /> - accessing one byte means we&#039;ll access the same byte nearby in time<br /> <br /> <br /> Hardware manages level 1-3 caches, TLB (generally)<br /> compiler manages CPU registers<br /> OS kernel manages main memory and disk<br /> <br /> <br /> What would be the optimal algorithm for managing main memory?<br /> - predict future<br /> - throw out data that won&#039;t be used, load data that will be<br /> <br /> In practice, we mostly use LRU (least recently used)<br /> - if you haven&#039;t accessed it recently you probably won&#039;t in the future<br /> <br /> Memory is managed in fixed-sized chunks always<br /> - reduces overhead<br /> <br /> Typically 4K or 8K, but can be multiple megabytes<br /> <br /> If it is on disk, it is a block<br /> If it is in RAM, it is a page<br /> <br /> Page table<br /> - data structure that maps virtual to physical memory,<br /> at page-level granularity<br /> <br /> each process has its own page table<br /> <br /> CPU (the MMU part) walks the page table to map virtual to physical addresses<br /> - and caches results in the TLB<br /> <br /> pages (virtual pages) are stored in frames (physical memory)<br /> <br /> when the CPU finds nothing corresponding to a virtual address, the OS gets called<br /> &lt;/pre&gt;</div>

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